1. Field of the Invention
This invention relates to semiconductor fabrication, and more particularly to a method for forming a shallow trench isolation (STI) structure without microscratches so as to reduce a dishing effect during a planarization process.
2. Description of Related Art
The purpose of an isolation structure in an IC device is to prevent carriers, such as electrons or electron holes, from drifting between two adjacent device elements through a semiconductor substrate to cause a current leakage. For example, carriers drift between two adjacent transistors through their substrate. Conventionally, isolation structures are formed between field effect transistors (FETs) in an IC device, such as a dynamic random access memory (DRAM) device, to prevent a current leakage from occurring. The isolation structures usually are formed directly on the semiconductor substrate. For example, a local oxidation (LOCOS) process is a typical isolation process widely used to form a field oxide (FOX) structure for isolating a metal oxide semiconductor (MOS) transistor. LOCOS technology has been well developed so that it can effectively isolate the MOS transistor with a good reliability of performance and low fabrication cost. However, LOCOS technology still has some problems. One example is an occurrence of a bird's beak on the edge of the FOX structure. The bird's beak reduces the isolation performance when device dimension is reduced. Hence, LOCOS technology is not suitable for a highly integrated device.
Shallow trench isolation (STI) is another widely used technology for isolating device elements. The STI structure is particularly suitable for a highly reduced dimension. The STI process usually uses a silicon nitride layer as a mask to form a trench in the substrate by anisotropic etching. Then the trench is filled with an oxide material serving as an isolating structure which has a top surface as high as the substrate surface.
FIGS. 1A-1C are cross-sectional views of a semiconductor device schematically illustrating a conventional fabrication process for forming a STI structure. In FIG. 1A, a masking layer 102 with desired pattern is formed over a semiconductor substrate 100. A trench 104 is formed in the substrate 100 by etching. In FIG. 1B, an insulating layer 106 including oxide is formed over the substrate 100 so that the trench 104 is filled.
In FIG. 1C, a chemical mechanical polishing (CMP) process is performed to polish the insulating layer 106 until the masking layer 102 is exposed, in which the remaining portion within the trench 104 lorms a STI structure 106a.
The CMP process is performed by using the masking layer 102 as the polishing stop layer. In order to completely remove the insulating layer on the masking layer, a strategy of over-polishing the masking layer 102 is usually taken. Since the masking layer 102 is usually harder than the insulating layer 106, the insulating layer 106 has a faster polishing rate than that of the masking layer 102. This causes the STI structure 106a to have a concave surface, which is lower than the top surface of the masking layer 102. This phenomenon is also called a dishing phenomenon. If the width of the trench 104 gets wider, the dishing phenomenon becomes more obvious and may cause a dishing problem. Moreover, because the CMP process includes small grinding particles to polish the insulating layer 104, microscratches may occur on the surface of the STI structure 106a. Furthermore, the polished surface of the substrate 100 may not be uniform due to global planarization. All these problems can affect the performance of the semiconductor device.